Programmed timing circuits



Dec. 12, 1967 F. W. WEBER 3,358,236

PROGRAMMED TIMING CIRCUITS Fil-ed April l2, 1965 5 Sheets-Sheet 1 xl m u A,

Q SN w51' g wx H@ INVENTOR.

Dec. 12, 1967 F. W. WEBER 3,358,236

PROGRAMMED TIMING CIRCUITS IN VENTOR. ffm/ W M/ffe Dec. 12, 1967 F.w. WEBER 3,358,236

PROGRAMMED TIMING CIRCUITS Fued Apri1 12, 1965 5 Sheets-Sheet 3 INVENTOR Dec- 12, 1967 F. wv WEBER 3,358,236

PROGRAMMED TIMING CIRCUITS Filed April l2, 1965 5 Sheets-Sheet 4 ai); I` 'f7/'Mza' INVENTOR,

I BY/fi, #5.535%

Dec. 12, 1967 F. W. WEBER 3,358,236

PROGRAMMED TIMING CIRCUITS auf new 0 im 55 -754 el/E l I I Fem/ H/ Wage United States Patent Oice 3,358,236 Patented Dec. 12, .1.967

3,353,236 PROGRAMMED TIMING CIRCUITS Frank W. Weber, Duarte, Calif., assignor to Burroughs Corporation, Detroit, Mich., a corporation of Michigan Filed Apr. 12, 1965, Ser. N 447,170 16 Claims. (Cl. 328-58) ABSTRACT F THE DISCLGSURE Pulse generating circuits wherein the duration or delay tirne of output signals generated by the circuits is determined by input signals applied thereto which are representative of the logic condition of associated circuitry. The pulse generating circuits include timing capacitors, the charging and discharging of which determine the duration or delay time of the output signals. The input signals control the charging and discharging of the timing capacitors by controlling, in respective embodiments, the value of current passing through the capacitors, the resistive values of resistors associated with the capacitors, the Value of potential to which the capacitors charge, and the capacitive values of the capacitors.

This invention relates to improvements in electrical timing circuits and, more particularly, to such circuits in which particular resistance-capacitance networks used for timing control are selected by means of associated information signals.

Pulse generating circuits in which the pulse duration is controlled by means of a resistance-capacitance network are well-known. For example, a monostable multivibrator type circuit may be used to generate pulses of a specic duration controlled by the time constant, i.e., the product of the resistance R and capacitance C of an R-C network, and by the voltage differential through which the network discharges. In this type of circuit an input trigger pulse initiates a discharge-recharge cycle for the capacitor. The output pulse duration is generally controlled by the discharge time of the capacitor through the resistance of the discharge circuit, the output pulse and discharge time both commencing with the commencement of the trigger signal. Another type of pulse generating circuit which is widely used in electronic systems to delay a pulse signal for a predetermined time interval is the electronic delay circuit. In this type of circuit an input trigger pulse also initiates a discharge-recharge cycle for a capacitor in an associated resistance-capacitance network. The specific delay time is controlled by the time constant of the network and also by the voltage differential through which the network charges. Moreover, the output pulse duration in this type of circuit continues beyond the termination of the trigger signal for a period of time equal to the delay time of the circuit. The recharge time of the capacitor generally commences with the termination of the trigger signal.

In many electronic systems, such as digital data processors, for example, it is necessary to generate output pulses of several diierent specic time durations or to delay pulse signals by several different predetermined periods of time. The particular pulse duration or delay time desired may, for example, be dependent upon the electrical condition of associated logic circuitry or upon signals from one or more sources of control signals.

Delay circuits and multivibrator circuits generally include a normally open input switch, the operation of which is controlled by input signals applied thereto, and a normally closed output switch coupled to the input switch. Coupled between the input and output switches is control circuitry including a timing capacitor. The circuits generate an output signal whenever the normally closed output switch is opened. In typical multivibrator circuits, the timing capacitor commences to discharge upon the application of an input signal and an output signal is generated which commences with the application of the input signal and terminates with the discharge of the capacitor. In typical delay circuits, on the other hand, the timing capacitor discharges immediately upon application of an input signal and commences to recharge upon termination of the input signal. The output signal which is generated commences upon application of the input signal and terminates when the capacitor has become recharged.

An advantage of the present invention is that it enables a pulse generating circuit of the multivibrator type to produce output signals of any of several predetermined time durations dependent upon the presence or absence of signals applied to control circuitry associated with the multivibrator. The present invention enables the circuit to generate any number of pulses having different predetermined time durations.

Another advantage of the present invention is that it enables a delay circuit to generate output pulses of differing predetermined delay periods dependent upon the presence or absence of signals applied to control circuitry associated with the circuit. In this arrangement too the present invention enables the circuit to generate output pulses having any number of dilferent predetermined delay times.

The above and other advantages of the present invention are achieved by means of independent control of the time during which the timing capacitor maintains the normally closed output switch in an open condition. This control is achieved by means of changes effected in control circuitry connected to the timing capacitor. These changes in the control circuitry are in turn controlled by logic signals received from one or more associated circuits and may advantageously be representative of particular binary logical states assumed by the associated circuits. Thus, the presence of a particular signal may advantageously manivfest that its associated logic circuit is in a true condition while the absence of a particular signal may similarly manifest that its associate logic circuit is in a false condition. Such control of the time during which the output 'switch remains closed renders pulse generating circuits in accordance with the present invention programmable. Thus, the particular predetermined time durations exhibited by the output signals of such circuits may be made dependent upon the logical state of associated logic circuits.

It is well known that the time in which a resistancecapacitance network is charged or discharged under constant current conditions is governed by the relationship T=Q/I. Where T represents the time of charge or discharge, Q represents the initial charge from which the capacitor is discharged or the final value to which it is charged, and I represents a constant value of charging or discharging current. Additionally, it is known that the time in which the capacitor C of a resistance-capacitance network charges in response to the application of a potential across the network of Vs is given by the relationship T-RC 1n --VS V, K where Vs is the potential across the resistor R at the beginning of the charging period and Vs-V is the potential across the resistor R at the end of the charging period. Similarly, it is known that the time in which the capacitor C of a resistance-capacitance network discharges from one value of potential to another is given by the relationship T=RClnV/V where V' is the potential across the resistor R at the beginning of the discharge period and V is the potential across the resistor R at the end of the discharge period. Thus, it can be seen that predetermined changes in the value of I, R, C, or V will produce corresponding predetermined changes in T. The present invention achieves such predetermined changes in T by means of changes in I,- R, C, and V eiected by logic signals representative of lthe true or false conditions of associated circuits. As a result, the duration or delay time of output signals generated by timing circuits in accordance with the present invention may be made to be of any number of different predetermined time durations in -response to particular combinations of logic signals.

The manner of operation of the present invention and the manner in which it achieves the above and the 'other advantages may be more clearly understood by reference to the following detailed description when considered with the drawing, in which:

FIG. 1 depicts a multivibrator circuit in which logic signals effect discharge of a timing capacitor by several predetermined values of constant current;

FIG. 2 depic-ts pulse diagrams indicating output pulses generated by the circuit of FIG. 1 under several diierent input conditions;

l PIG. 3 vdepicts a delay circuit in which logic signals effect the charging of a timing capacitor through differentV v-alues of resistance;

FIG. 4 depicts pulse diagrams indicating output pulses generated by the circuit of FIG. 3 under several different input conditions;

FIG. 5 depicts a delay circuit in which logic signals effect the charging of several different timing capacitors;

-FIG. 6 depicts pulse diagrams indicating output pulses generated by the circuit of FIG. 5 under several different input conditions;

lFIG. 7 depicts a delay circuit in which logic signals effeet the charging of a timing capacitor to several diierent values of potential; and

FIG. 8 depicts pulse diagrams indicating output pulses generated by the circuit of FIG. 7 under several different input conditions.

Transistors are utilized as the active elements in each of the circuits depicted in the drawing. Although transistors make excellent switches, the present invention is not to be considered limited to timing circuits in which 'transistors are employed. The present invention is applicable to any timing circuit in which pulses generated at an output switch by means of signals applied to an input switch exhibit a delay time or dura-tion time dependent upon the state of control circuitry intermediate the input and output switches.

The transistor switches shown in the drawing are advantageously driven into saturation by input signals applied thereto to close the switches. When in a saturated condition, Ithe collector potential of a ltransistor is inter- .mediate its base potential and its emitter potential and is essentially equal to its emitter potential. Thus, when driven into saturation, the emitter and collector are at essentially the same potential and excellent switching action is therefore achieved.

FIG. l depicts a programmable multivibrator circuit in accordance with the principles of the present invention. I-t includes an input switch and an output switch, a timing capacitor coupled therebetween and control circuitary coupled to the capacitor for governing the period of the multivibrator.

The input switch includes a PNP transistor 10 having I an emitter 11, base 12, and collector 13. Emitter 11 is connected directly to a ground reference potential and collector 13 is connected through biasing resistor 14 to a source of negative potential represented 'as ,-V. The base 12 is connected through diode 15 to trigger Apulse source 16. The out-put switch includes a PNP transistor 17 having a base element 1S, emitter 19, and collector 20. The emitter 19 is also connected directly to ground potential while the collector 20 is connected through diode 21 and resistor 22 to the source of negative potential --V. Coupled between the -two switches is timing capacitor 23 connected between collector 13 of transistor 10 and base 18 of transistor 17. Additionally feedback diode 24 is connected between the junction of diode and source 16 and the junction of diode 21 and resistor 22. Collector Y of transistor 17 is also connected to the source of nega- Itive potential V through resistor 25. Output terminal 26 is located at the junction of collector 20 and resistor 25.

The control circuitry includes NP=N transistor 27 having a base element 28, emitter 29, and collector 30. Base 28 is connected to the junction of Voltage divider resistors 31 and 32 which are connected between ground potential and the source of negative potential -V. The collector 30 is connected to the junction of capacitor 23 and the base 1S of transistor 17. The emitter 29 is connected through resistor 33 to the source of negative' potential -V and is also connected via diode 34 to the collectorV 35 of 1PNP transistor 36. Transistor 36 has its emitter 37 connected directly to ground potential and its base 38 connected via diode 39 and resistor 40 Ito the source of negative Voltage -V. Collector 35 of transistor 36 is also' to a source of logic pulses 46 and its collector 47 con-r nected to the source of negative potential V through resistor 48 and Variable resistor 49. Additionally, collector 47 is connected to the junction of diode 39 and resistor 40 by diode 50. Finally, emitter 29 of transistorV 27 is also connected to the junction of resistor 48 and diode 50 by diode 51. The diodes are poled as depicted in FIG. 1.

Trigger pulse source 16 is shown in block diagraml form and may represent any well known circuit capable of applying negative signals to base 12 of transistor 10 suicient to saturate this transistor. Similarly, logic signal source 46 is shown in block diagram form and may represent any well known means for presenting signals to base 45 of transistor 43indicative of the state of associated logic circuitry. Advantageously, the true statey may be represented by a negative potential applied to base 45 sufficient to saturate transistor 43 while the false state is represented by ground potential applied to base 45.

In the operation of the circuit depicted in FIG. 1, transistor 27 is always maintained in the conducting state. This results since the base 28 of this transistor isheld at a constant negative potential of a value smaller than -V. by the voltage dividing resistors 31 and 32. Since emitter 29 of this transistor is connected to potential -V vvia resistor 33, the base 28 is held at a potential suflicient to maintain transistor 27 in the saturated conducting state. Transistor 17 is normally also in a conductive, state. Since base 18 of this transistor is connected to collector 30 of the always conductive transistor 27,V the base 18 is normally at a potential which is somewhat negative with respect to ground. As a result, transistor 17 will be in a saturated conducting state and its collector 20 willbe at ground potential. Similarly, output terminal 26 is also at ground potential.

Transistor Y10 is normally in a non-conducting state. However, upon the application of a negative trigger signal from pulse source 16 to its base element 12, this transistor is switched to the saturated conducting state. As a result, its collector 13which previously was at `a potential approximately equal to -V will, upon the switching of transistor 10, have ground potential applied thereto. This nearly instantaneous change in potential of collector 13g will be reflected across capacitor 2,3 to base 18 of transistor 17 thereby turning oi transistor 17.

The turning olf of transistor 17 removes ground potential vfrom its collector 2f) and output'l terminal 26, thereby enabling the source of negative potential -V to establish a negative output signal at output terminal 26.

This output signal will exist for the delay period of the multivibrator circuit. The length of this delay period is determined by the presence or 1absence of a signal applied from pulse source 46, as described hereafter.

The diode 24 connected between the junction of diode and trigger pulse source 16 and the junction of diode 21 and resistor 22 serves to maintain transistor 10 in the conducting condition subsequent to the termination of the pulse from source 16 and for as long as transistor 17 remains non-conducting. Diode 24 thus maintains base 12 of transistor 10 at a negative potential throughout the delay period of the multivibrator.

During the delay period of the multivibrator shown in FIG. 1, transistor 10 remains in the conducting condition and transistor 17 in the non-conducting condition. During this period capacitor 23 discharges. Upon the discharge of capacitor 23, base 18 of transistor 17 will again reach a potential which is negative with respect to ground and transistor 17 will revert to its conducting state. As a result, a negative voltage su'icient to hold transistor 10 in a conducting state will no longer be coupled to base 12 of transistor 10 by diode 24 and the transistor 10 will revert to its non-conducting state. The length of time required for the discharge of capacitor 23 is dependent on the presence or absence of a negative signal from source 46.

If the absence of a negative signal from source 46 is assumed to indicate that associated logic circuitry is in a false condition, then capacitor 23 will discharge through the parallel combination of resistance 33 and series resistances 48 and 49. If, on the other hand, a negative signal is applied from source 46 indicating that associated logic circuitry is in the true condition, then, as described hereinafter, capacitor 23 will discharge through the parallel combination of resistance 33 and series resistances 41 and 42. The time in which capacitor 23 discharges and the consequent delay time of the multivibrator circuit is dependent upon the values of resistance through which it discharges and hence may be made to depend upon whether the associated logic circuitry is in the true or false condition. In the absence of a negative from source 46 transistor 36 will be conductive since a negative signal will be applied to its base element 38 by means of diode 39, resistance 40, and the source of negative potential V.

With transistor 36 in a conducting state, its collector element 35 will have a potential essentially equal to ground potential impressed thereon and discharge current from capacitor 23 will therefore be directed via diode 51 through resistors 48 and 49, as Well as through resistor 33.

If, on the other hand, a negative signal from source 46 is applied to base 45 of transistor 43, this transistor will be rendered conductive and its collector element 47 will have a potential essentially equal to ground potential impressed thereon. Diode 39 is selected such that this diode has a substantially greater potential drop than does diode 50. This would be true for example if diode 39 were a silicon diode and diode 5t) were a germanium diode. Since collector 47 is at ground potential as a result of transistor 43 being conducting, the necessary voltage drops across diodes 39 and 50 therefore cause transistor 36 to become non-conducting. As la result, capacitor 23 will discharge both through resistor 33 and the resistors 41 and 42, when associated logic circuitry is in the true condition.

The rischarge of capacitor 23 will, whether the signal from siurce 46 is of a negative potential indicative of a.

true condition or of ground potential indicative of a l false condition, be a constant current discharge since emitter 29 of transistor 27 is maintained at a constant potential during discharge. The discharge time may then Ybe determined from the equation:

6. where T is the delay time of the multivibrator circuit, Q is the initial charge upon capacitor 23, I1 is the current through resistor 33 `and I2 is the current through resistors 48 and 49, or through resistors 41 and 42, as the case may be. Thus, by adjusting the values of these elements, various delay periods can be achieved. In particular, by making the sum of resistirs 41 and 42 one particular value and the sum of resistors 48 and 49 a different particular value, different delay times can be achieved dependent upon associated logic circuitry being in either a true or a false condition. Small adjustments in these delay periods may be achieved by means of adjustments made to the resistors 42 and 49.

Operation of the multivibrator of FIG. 1 may be more clearly understood from the pulse diagrams shown in FIG. 2. FIG. 2 indicates the logic signals from source 46, trigger pulses from source 16 and output signals applied to terminal 26. The logic pulse source will at all times be in either of two conditions, indicative of associated logic circuitry being either true or false at any given time. These conditions may be considered as being tWo distinct signals applied to transistor 43. Thus, as shown in FIG. 2, a negative signal from source 46 is indicative of associated circuitry being in the true condition while ground potential is indicative of associated circuitry being in the false condition. Two trigger pulses from source 16 are also indicated in FIG. 2, one occurring when the source 46 indicates a true condition and the other occurring when the source 46 indicates a false condition.

FIG. 2 also indicates output signals appearing at terminal 26 in response to these two trigger pulses. Thus, a first output pulse is shown in response to the rst trigger pulse occurring when source 46 indicates the true condition and a second and substantially longer output pulse is shown in response to the second trigger pulse occurring when source 46 indicates a false condition. Thus, it is seen that two substantially dierent output signals will appear at terminal 26 with the particular signal deterl mined by the presence or absence of a negative signal from source 46.

It may be noted that the duration of each of the output pulses indicated in FIG. 2 is xed. Thus, each output signal commences upon the commencement of a trigger pulse and lasts for a predetermined time measured from the commencement of the trigger pulse.

, In the circuit of FIG. 3, however, it will be seen that output pulses will also have a xed delay time associated therewith but that this delay time will be measured from the termination of associated trigger pulses rather than from their commencement. Thus, the circuit of FIG. 3 is a delay circuit rather than a multivibrator circuit.

FIG. 3 depicts a programmable delay circuit in accordance with the principles of the present invention. This circuit includes a normally non-conducting PNP transistor 60 having its emitter 61 connected directly to ground, its base 62 connected to a source of trigger p-ulses 63 and its collector 64 connected through resistor 65 to a source of negative potential V. It also includes a normally conducting NPN transistor 66 having its base element 67 connected to the junction of serially connected resistors 68 and 69 connected between the source of negative potential -V and ground, respectively. Transistor 66 has its emitter 70 connected to the collector element 64 of transistor 60, and has its collector 71 connected to the base 72 of a normally conducting PNP transistor 73. Transistor 73 has its emitter 74 connected to ground and its collector element 75 connected via resistor 76 to the source of negative potential -V and also connected to output terminal 77. A resistor 78 and a diode 79" are both connected between the junction of collector 71 and base 72 and to a source of positive potential -l-V and ground potential, respectively. A timing capacitor 80 is connected between ground potential and the junction of emitter 70 of transistor 66 and collector 64 of transistor 60. Transistor 60 may be considered a normally open input switch while transistor 73 may be considered a normally closed output switch.

A PNP transistor 81 has its emitter 82 connected directly to ground, its base 83 connected to a source of logic signals 84 and its collector 85 connected through resistor 86 andvariable resistor 87 to the source of negative potential- -V. A PNP transistor 88 has its emitter 891' connected directly to ground, its base 90 connected via diode 91 and resistor 92 to the source of negative potential -V' andl its collector 93 connected through resistor 94 and variableresistor 95 to the source of negative potential -V. A diode 96 connects thejunction of collector SSfand'resistor S6 to the junction of diode 91 and resistor 92. The junction of collector 64 of transistor 60 and resistor 65- is connected to the junction otresistor 86 and diode'96 by diode 97 to the junction of collector 93 and resistor 94' by diode 98".

The trigger pulsejsourcell and logic-signal source 84Y are shown in block diagram form and may represent any well known circuitry capable-of performing theV functions performed by the similar sources 16 and 46-discussed in connection with the circuitl shown in FIG. l.

Asstated previously, thetransistors-66 and' 73 will beY normally conducting while the transistor 60'. will be normally non-conducting. Transistor 66 will be' normallyconducting sincev its` base 67 will be held at a negative potent'i'al smaller than -V asy determined by the voltage divider action of resistors 68 and 69 Whereas its emitter 70 will be ati a considerably more negative voltage as'determined by' resistor 65- andthe source of negative potential -V since transistor 60 is normally non-conducting.

The effectV of transistor 66 being in a conducting state is to` maintain' transistor' 73 also` in a conducting state. This results sincecon'duction within transistor 66 presents a negative voltagel to the base' 7210i transistor 73, thereby rendering transistor 73 conducting. Conduction within transistor 73 establishes groundy potential at its collector 75 which' signall is transmitted tooutput terminal 7T.

A negative signalJ appliedto base4 62 of transistor 60 from pulse source 63 will render' transistor 60 conducting thereby` establishing a potential essentially equal to ground potential at' collector'64 in turn shuttingoi transistor 66 and transistor 7-3. Transistor 66 shuts` on since its base.v potential will nowv beY negative relative to its emitter potential and transistor 73- shuts 0E since its base potential be rendered positive relative to` its emitter potential` by resistor 78and they source of positive potential +V. Capacitor 80 will' at this time completely discharge.

Upon termination of the pul'sefrom source 63g transistor 6W will shut oflv and at this time none of the three transistors 60, 66, and '73 will bel conducting. I-f the circuitry associated with transistors 81 and 88 is neglected for the moment, capacitor 80 will at this timey commence to` charge throughresistor" 65 toward potential -V. CapacitorA 80 will not reachthe potential --Vv because tran sistors 66 and 73 will again be rendered c-:onduct-ingy when capacitor 80r is charged to a negative potential less than -V Thus, Whenever the capacitor reaches a potential somewhat more negative than that established on base 67 by' the voltage divider resistors- 68 and 69, transistors 66 and 73 will again be rendered conductive.

The time Within which capacitor 80 is charged to a value sufficient to turn on transistors 66 and 73 is governed by the equation V T Rein where R is the resistance of resistor 65, C is the capacitance of capacitor 80, V is the value of voltage applied by the source of negative potential -V and V' is the voltage across capacitor 80 when transistors 66 and 73 again becomes conducting.

During the time the transistor 73 is non-conducting its collector 75 will he at a negative potential equally equal ,to -V and this negative potential will be transmitted to output terminal 77. Thus, this negative output signal will be applied to terminal 77 commencing with the application of a pulse from source 63 to transistor 60 and terminating when capacitor 80 becomes suiliciently charged to again turn on transistors 66 and-73.

It may be seen that While the delay period of the circuit in FIG. l was determined by the length of time required todischarge a capacitor, the delay period ofl the circuit of FIG. 3 is determined by the length of time required to-charge a capacitor. Moreover, in the circuit of FIG. 3,

this time is measured from thel termination of a pulse from source 63 rather than from the moment of initial application of a pulse from source 63.

The circuitry associated with transistors 81 and 88 of FIG. 3 may be utilized to varyfthe length of time required to charge capacitor 80 suficiently to turn on transistors 66 and 73. A signal from source 84 will, as did signal source 46 in FIG. l, apply a negative signal to the base 83 of transistor 81 sufficient to turn on this transistor when associated logic circuitry is in the true condition. Similarly, ground potenti-al will be applied to transistor 81 by source 84 when the associated logic circuitry is in the false condition. If groundy potential isV appliedv by source 84, transistor 81 will be non-conducting and transistor 88 will be conducting. Transistor 88 will conduct since a negative signal will be applied to its base element 90 via diode 91 and resistor 92. Conduction of transistor 88 will establish at its collector 93 a potential substantially equal to groundy potential whereas the potential at the junction of diode 97 andA resistor 86 will be substantially negative. As a result capacitor 80A will charge through resistor 86 and variable resistor 87 as vvell as through resistor 65, and the time Within which capacitor 80: is suiciently charged toturn transistors 66 and 73 will be governed by the parallel combination of these reslstances.

If, on the other hand, a negative signal is'applied from source 84 to transistor 81, transistor 81Will be rendered conducting and its collector 85 Will have a potential established.' thereon essentially equal' to ground potential. Transistor 88 will at this time be turned oi. Diode 91- is selected tohave la substantially greater potential drop than does diode 96. Diode 91 may, for example, be a silicon diode whereas` diode 96 may be a germanium d iiode.Y Diodes 96 and 91 thereforeassure thatthe potent1al. of base 90 of transistor 88 willV be positive relative to emitter 89? whenk transistor 81 is conductive, therefore cutting off transistor 88; With transistor 88'4 non-conductlng, collector 93 will be at a potential which is sub- Stantially negativewith` respect to ground whereas the junction of diode 97 and resistor 86 will be ata potential substantially equal to ground potential. As a result, capacitor 80 will charge through resistor 94v and variable resistor 9,5 as Well as through.` resistor 65 Whenever a negative signal isappliedto transistor 81 from source 84'.

T he: time in which capacitor 80 charges su-iciently to again turn on transistors 66 and 73 will then bey governed 1n partby the parallel combination of resistors 65, 94- and 9 5. Thus, it may be seen that the delaytime ofthe circuit shown in FIG. 3f may be made to vary dependingupon the presence or absence ofV a negative signal from source 84. suicientto render transistor 81 conducting.

The operation of the circuit of FIG. 3 is further de` picted` by the pulse diagrams shown in FIG; 4. Thus, a negative signal` from sourcev 84y is shown to indicate that associated logic circuitry. is inthe true conditionwhile ground potential is shown to indicate that associated logic circuitry is inthe false condition. Two trigger pulses from source 63 are also shown inV FIG. 4, one occurring when theassociated logic circuitry is in the true condition andthe otherv occurring when it is in the false condition. Finally, two output pulses are shown in FIG. 4 occurring in response to the two trigger pulses. The rst output pulse is shown to commence upon the application of the trigger pulse and to continue for a time Tt after the termination of the trigger pulse. The time Tt is the delay time of the circuit of FIG. 3 and would be determined in part by the combined parallel resistance of resistors 65, 94 and 9S. A second output pulse is shown in FIG. 4 to commence upon the application of the second trigger pulse and to continue for a period Tf after the termination of the second trigger pulse. This time Tf may be considerably different from the time Tt as shown in FIG. 4 and will be determined in part by the combined parallel resistance of resistors 65, 86 and 87. Thus, it may be seen that the delay time of an output signal appearing at output terminal 77 may be made dependent upon associated logic circuitry being in the true or false condition. Smaller adjustments in the delay time may be made by means of the variable resistors 87 and 95.

The circuit of FIG. 5 depicts a modiiication of the programmable delay circuit of FIG. 3. Elements appearing both in FIG. 3 and FIG. 5 are denoted by the same reference characters in both gures. Thus, transistors 60, 66, and 73 are shown in both FIG. 3 and FIG. 5. FIG. 5, however, depicts two timing capacitors 101 and 102 rather than the single capacitor 80 of FIG. 3. Capacitor 101 is connected between collector 64 of transistor 60 and collector 103 of PNP transistor 104. Transistor 104 has its emitter 105 connected directly to ground and its base 106 connected to a source of logic signals 107. Collector 103 is also connected to ground via diode 108. Capacitor 102 is connected between collector 64 of transistor 60 and collector 109 of PNP transistor 110. Emitter 111 of transistor 110 is connected to ground and its base 112 is connected to a source of logic signals 113. Collector 109 of transistor 110 is also connected to ground via diode 114.

As in the circuit of FIG. 3, transistors 66 and 73 are normally conducting whereas transistor 60 is normally non-conducting. A pulse from the trigger pulse source 63 similarly renders transistor 60 conducting and transistors 66 and 73 non-conducting. Y

Neglecting capacitors 101 and 102 for the moment, it may be seen that transistors 66 and 73 would be rendered conducting immediately upon the termination of a pulse from source 63. Thus, there would be no delay in the output signal applied to output terminal 77. If, however, a negative signal is applied from source 107 to transistor 104, this transistor will be .rendered conducting and its collector 103 will be at a potential essentially equal to ground potential. Thus, capacitor 101 will, during the application of a negative signal from source 107 be connected between collector 64 of transistor 60 and ground potential just as was capacitor 80 of FIG. 3. A delay time will therefore be introduced into the circuit of FIG. 5 which delay time will be dependent upon theY charging of capacitor 101 through resistor 6 5.

If, however, a negative signal is applied to transistor 110 from source 113, this transistor will be rendered conducting and its associated capacitor 102 will essentially be connected between collector 64 of transistor 60 and ground potential. Thus, if a negative signal from source 113 is applied to transistor 110 in the absence vof a pulse from source 107 to transistor 104 the delay time of the circuit of FIG. 5 will be dependent upon the time in which capacitor 102 charges through resistor 65 su'ciently to turn on transistors 66 and 73.

The delay time in the two situations just described is dependent upon the capacitance value of the capacitors 101 and 102. Thus, it may be seen that by making capacitors 101 and 102 of diiering capacitance value the delay time of the circuit of FIG. 5 may be made to be of one value when a negative signal is applied from source 107 in the absence of a negative signal from source 113 and of a diierent value when a negative signal is applied from source 113 in the absence of a negative signal from source 107. Similarly, if negative signals are applied from both sources 107 and 113, the circuit of FIG. 5 will exhibit a third delay time differing from either of the first l0 two and dependent upon the capacitance value of the two parallel connected capacitors 101 and 102. Thus, for example, if capacitor 102 has a capacitance value twice that of capacitor 101, a negative signal from source 107 will introduce a delay time of one unit into the circuit of FIG. 5, a negative signal from source 113 will introduce a two unit delay time into the circuit of FIG. 5, and combined negative signals from both sources 107 and 113 Will introduce a three unit delay time into the circuit of FIG. 5.

It may be noted that the diodes 108 and 114 are poled to permit the discharging but not the charging of the timing capacitors via these diodes. Thus the charging of the capacitors and consequently the delay time of the circuit shown in FIG. 5 is dependent upon the state of logic circuitry associated with sources 107 and 113.

The pulse diagrams shown in FIG. 6 illustrate the operation of the delay circuit shown in FIG. 5. Again negative signals from sources 107 and 113 are indicative of their associated logic circuitry being in the true condition whereas ground potential signals from these sources are indicative of their associated logic circuitry being in the false condition. Four signals from trigger pulse source 63 are shown in FIG. 6. One occurs during the presence of a negative signal from source 107 and in the absence of a negative signal from source 113 thereby producing an output signal having a delay time indicated by T2. A second trigger pulse from source 63 occurs in the absence of negative signals from either source 107 or source 113 thereby producing an output signal having no delay time. A third pulse from trigger pulse source 63 is shown to occur in the presence of a negative signal from source 113 and in the absence of a negative signal from source 107 thereby producing an ouput signal having a delay time of T1. Finally, a fourth trigger pulse from source 63 is shown to occur in the presence of negative signals from both sources 107 and 113 thereby producing an output signal having a delay time of Trl-T2.

FIG. 7 depicts another modification of the delay circuit shown in FIG. 3. Again elements common to both figures will be given the same reference characters. Base 67 of transistor 66 instead of being simply connected between voltage divider resistors 68 and 69 as in FIG. 3 is shown in FIG. 7 to be connected at the junction of resistor 68 and series connected resistors 69a, 69h and 69e. The collector 121 of PNP transistor 122 is shown in FIG. 7 to be connected at the junction of resistors 69a and 69b. Similarly, collector 123 of PNP transistor 124 is connected to the junction of resistors 69h and 69e. Emitter 125 of transistor 122 is connected directly to ground while f base 126 of this transistor is connected to source of logic pulses 129. Emitter 130 of transistor 124 is also connected directly to ground and base 131 of this transistor is connected to source of logic pulses 134.

In a manner similar to the delay circuit described in conjunction with the discussion of FIG. 3, transistor 60 will be normally non-conducting while transistors 66 and 73 will be be normally conducting. Thus, an application of an input signal from trigger pulse source 63 renders transistor 60 conducting and transistors 66 and 73 nonconducting, and causes the discharge of capacitor 80. Upon the removal of the trigger pulse from source 63 capacitor 80 commences to charge and when it reaches a potential slightly greater than the fixed potential of base 67 of transistor 66, both transistors 66 and 73 will again be rendered conducting. Whereas in the circuit of FIG. 3 the potential applied to base 67 of transistor 66 was a constant value independent of the application of logic signals from source 84, the potential of base 67 of transistor 66 in FIG. 7 is not independent of logic signals applied from sources 129 and 134. Thus, if pulses are applied from neither source 129 nor from source 134, base 67 will be held at one particular value of potential and transistors 66 and 73 will be rendered conducting when capacitor 80 charges to this particular value.

If, however, a negative signal is applied from source 129 to transistor 122, this transistor will be rendered conducting. Since' the signal from source 129 will be suficient to saturate transistor 122, its collector 1-21 will be at a potential valve essentially equal to ground potential. Thus, the junction between resistors 69a and 69b will be at ground .potential and the voltage divider action of resistors 69a and 68 will establish a potential at the base 67' of transistor 66 which is substantially lower than that established at this point inthe absence of a signal from source 129; Thus, transistors 66 andl 88 will begin conducting upon capacitor 80 charging to a much smaller potential than previously and the delay time of the output signal presented to output terminal 77 will be' substantially smaller than in the absence of the signal from source 129.

If, on the other hand, a negative signal is applied to transistor 124 from source 134 rather than to transistor 122 from source 121, transistor 124 rather than transistor 122l will be rendered conducting. Since this transistor will alsofbe driven into saturation, its collector 123 will also have a potenti-al essentially equal to ground potential irnpressed thereon and the junction of resistors 69b and 69e` will be set to ground potential. As a result of the voltage divider action of resistors 68 and resistors 69a and 69h, a stillJ diierent potential will now be applied to base 67 of transistor 66. This potential will be smaller than that impressed upon this point in the absence of signals from either source 129 or 134 but larger than that upon this point iny response to a signal from source 129. As a result, transistors 66 and 88 will be rendered conducting by the chargingl of capacitor 86 to a value' intermediate of values in the two cases previously described.

The delay time of the circuit of FIG. 7 is thus dependent upon the presence or absence of signals from sources 129 and 134; This delay time will be greatest in the absence of signals from either of these sources, somewhat shorter in the' presence of a signal from source 134 and shortest in the presenceof a signal from source 129; The signalY presented totransistors 122 and 124by sources 129 and 134 will advantageously again reflect the condition of logic circuits associated with these circuits.

The operation of the circuit of FIG; 7 may be more clearly'understoody by the pulse diagrams shown in FIG; 8^. Source 129 is shown in FIG; 8 to produce a negative signal indicative of' a true condition in its associated logic circuitry' somewhat previously to a similar output signal produced by source 134l indicative of a true condition of its associated logic circuitry. Trigger pulse source 63 is` shown' toV produce a rst trigger pulse in the absence of negative signals from either source 1'29 or source 134, a second trigger pulse in the presence' of a negative signal from source 129k and a third trigger pulse in the presence of a negative signal from source 134. Output signals` presented to output terminali 77 inresponse to these trigger signals are also indicated. The output signal in response to the iii-st triggerv signal is shown to manifest a delay time:r to- The. output signal. in-` response to the second trigger' signal. is; shown to manifest a delay. time; t1` and; the output signal in responseY to the third trigger signal. is shownto manifest a. delay time t2. In accordance with the previous discussion of the circuit of FIG. 7', t0 is shown to be oi a time duration longer than that of either t1y or f2 whileftz is shown to beofa dur-ation longer thanthat of t1.

Several. embodiments of the present invention havebeen described. In,v each case the time of charging or discharging of a capacitor has been controlled by the application of one or more signals indicative of the state of associated logic circuitry. Thus, in the circuit of FIG. 1 discharge of capacitor 23" Was achieved by means of Ia constant current discharge. The time in which the capacitor discharged fromv an initial Xed value'was dependent upon the conistant value of current within the collector to emitter path of' transistor 27 which in turn was dependent upon the presence orV absence of a negative signal from source 46.

12 The delay times of the circuits of FIGS. 3, 5, and 7were -all dependent upon thetime in which one ormore capacitors charged' to a particular value. This time is dependent upon the value of resistance in the path through which the `capacitor charges, the value of the capacitance, and' theA value of the potential to which thecapacitor charges. All three of these variables ywere utilized to vary the delay timesin the circuit of FIGS. 3', 5, and 7; Thus, in FIG.'3 the value of resistance in thepath through which capacitor charges is made to dependl upon the presence or absence of a negative signalv from sourceV 84. In FIG. 5, the capacitive value ofthe charging capacitor is made todepend upon the' presence or absence of negative signals from sources 107 and 113, and. in FIG. 7 the Value of the potential to which capacitor 80 charges is made to depend upon the presence or absence of negative signals from sources 129' and 134.

The four means of varying the time in which a capacitor charges or discharges mayall be used'either singly or in combination inpulse generating circuits to-produce output signals ofl varying predetermined duration or of varying predetermined delay time; Additionally, thel present invention mayfbe utilized in connection With pulse generating' circuits other than those described herein. Thus, for example, it could be used in conjunction with the delay circuit disclosed in my Patent No. 3,132,261, issued May 5, 1964, or in conjunction with the multivibrator circuit disclosed in myPatent No. 3,171,978, issued Mar. 2, 1965, onan yapplication bearing Ser. No. 138,795', tiled on Sept; 18 1961, and assigned to the assignee of the* present invention.

What have been describedj are considered to be only illustrative embodiments' ofthe present invention and", accordingly, it is to be understood that various and numer ous other arrangements-may be devised" by one skilledV in the art Without departing from theY spirit and scope o this invention.

What is claimed is:

1. An electrical circuit comprising:

a normallyA open input switch having a rst input terminal,'the input switchY beingclosed in response to an input signal appliedl to the' first` inputterminal,

-anormally closed output switch coupled to the` input switch,

means coupled to4 the outputf switch for opening the output switch iny response t'o the closingV of the input switch,

timing circuit' means coupled to` both thev input switch and the output'switch and having ay first and ya second control circuit elementand a second inputA terminal,

means coupledl to the output switch for maintaining the outputy switch inv its open conditionl for a period of time governed bythe timing circuit means,

means coupled to the timing circuiti meansforisolating the rst control'vcircuitE element from the remainder of the timingv circuit'means-i'n response to a first signal? applied to the secondy inputl terminal, and

means coupled'to they timing circuit means for isolating the second controlA circuit' element from the remainder of the timing circuit means inY response to a second signal'f applied'I tothe second' input terminal.

2. An electrical circuit comprising:

a normally open input switch having a' 'rst input terminal, the input switch being closed'in response to aninput signaltapplied to the rst input' terminal,

a normally closed outputV switchr coupled to the' input switch,

a timingcapacitor coupledY to both the input switch and output switch,

abiasing resistor coupled to both the input switch and output switch, Y

the capacitor charging through the biasing resistor to a predeterminedirst value of potential when the input switch is open,

means coupled to the output switch andv including the 13 timing capacitor for opening the output switch in response to the closing of the input switch,

a feedback path connected between the input switch and the output switch for maintaining the input switch,

a timing capacitor coupled to both the input switch and output switch, the capacitor discharging when the input switch is closed and charging when the input switch is open,

means coupled to the output switch for opening the output switch in response to the closing of the input switch,

a biasing resist-or coupled to both the input switch and switch in a closed condition while the output switch output switch, is in an open condition, a first and a second charge path coupled to the timing a first and a second discharge path coupled to the timing capacitor,

capacitor, a second input terminal coupled to the first and second a second input terminal coupled to the first and second charge paths,

discharge paths, the capacitor charging through the biasing resistor and the capacitor discharging through the first discharge the first path toward a predetermined first value of path responsive to the presence of an input signal potential responsive to the presence of an input sigapplied t0 the second input terminal, nal applied to the second input terminal, the capacitor discharging through the second discharge the capacitor charging through the biasing resistor and path in the absence of a signal applied t0 the Second 15 the second path toward the predetermined first value input terminal, and of potential in the absence of an input signal applied 'means coupled to the output switch for holding the outto the Second input terlninal, and

put switch in an open condition until the capacitor IneanS coupled t0 the output SWitch for holding the discharges to a predetermined second value of potenoutput switch in an open condition until the capacitor tial. charges to a predetermined second value of potential. 3. An electrical circuit comprising: 6- An electrical circuit coniprising a normally open first transistor switch having a first a normally open first transistor switch having a first input terminal, the input switch being closed in input terminal, the first switch being closed in reresponse to an input signal applied to the first input spouse t0 an input signal 'applied to the first input terminal, terminal, a normally closed second transistor switch coupled to a normally closed Second transistor Switch coupled to the nrst switch, the first switch, a timing capacitor coupled to both the first and second a timing capacitor coupled to 'both the iirSt and SeC- switches, ond switches, the capacitor discharging when the first 'a biasing resistor coupled to both the first and second 30 Switch is closed and Charging When the first SWitch iS switches, open, the capacitor charging through the biasing resistor to a -lneans coupled to the Second SWitch for opening the predetermined val-ue of potential when the first switch Second sWitch in response to the closing of the lirst is open, switch, means including the timing capanitor for Opening the a biasing resistor coupled to both the nrst and second second switch in response to the closing of the first switches switch, a first and a second charge path coupled to the timing a feedback path connected |between the first switch and capacitor,

the Second switch for maintaining the rst switch in third and fourth transistor switches coupled to the first a closed condition while the second switch is in an 40 and Second charge Paths, open condition, logic circuit means coupled to ,the third and fourth a first and a second discharge path coupled to the timing Switches for maintaining one of the third and fOurth capacitor, switches open and the other closed, third and fourth transistor switches coupled to the first the capacitor charging through the biasing resistor and and Second discharge paths, 45 the first path toward a predetermined first value of logic circuit means coupled to the third and fourth Potential When the third switch is closed and charging switches for maintaining one of the third and fourth through the biasing resistor and the second Path t0- switches open andthe other closed, ward the predetermined first value of potential when the capacitor discharging when the first switch s closed, the fourth switch ,is closed, and I the capacitor discharging through the first discharge means coupled t0 the Second switch for holding the path when the third switch is closed and discharging Second switch in an open condition until the capacitor through the second discharge path when the fourth charges to a predetermined second Value'of Potentialswitch is closed, yand 7. An electrical circ-uit according to claim 6 in which means coupled to the second switch for holding the the biasing resistor, the first charge Path; and the Second second switch in an open condition until the capacitor char ge Path are ail connected in Parallel 'between the holddischarges to a predetermined second value of potening means and a Point maintained at the predetermined tial. first Value of potential. l .4. An electrical circuit according to claim 3 further com- S. An electrical circuit according to claim 6 in which prrsrng a fifth transistor switch coupled to the timing the holding means comprises: capacitor and included within lboth the first and second Va fifth transistor switch, dlscharge Paths, and I t means coupled to the fifth switch for opening the fifth means coupled to the f irth transistor switch for nianlswitch in response to discharge of the capacitor below taining the transistor switch 1n a closed condition a particular value of potential with its tranS1.stOr Saturted tileeby eiecimg con' means coupled to the fifth switch for closinv the fifth stant current discharge or the trmtng capacitor. Switch in res o t h f h e h 5. An electrical circuit comprising: p use o c arg1 ng o t e clpacltor to t e a normally open input switch having a first input terp redetermmed Second value of .potentlal minal, the input switch being closed in response to means coupied t9 the second Swltch f0.r opening the an input Signal applied to the first input terminal second switch 1n response to the opening of the fifth a normally closed output switch coupled to the input swltch and means coupled to the second switch for closing the second switch in response to the closing of the fifth switch.

9. An electrical circuit according to claim 6 in which the closing of the first switch in response to an input signal l applied to the first input terminal establishes a short circuit across the timing capacitor.

10. An electrical circuit comprising:

a normally open input switch having a first input terminal, the input switch being closed in response to an input signal applied to the first input terminal,

a normally closed output switch-coupled to the input switch,

a-iirstV timing'` capacitor coupled to both the input switch and output switch, the capacitor discharging when the inputswich is closed,

means coupled-to the' output switch for opening the output switch in response to the closing of the input switch,

a biasing resistor coupled to -both the input switch and output switch,

a normally open first control switch coupled to the first timing capacitor,

the control switch having a second. input terminal and being. closed in response tov an input signal applied to the second input terminal,

the rst timing capacitor charging through the biasing resistor toward a predetermined rst value of potential when the first control switch is closed, and

means coupled to the outputswitch for holding the output switch in an open condition until the rst capacitor charges to a predetermined second value of potential.

11. An electrical circuit according. to claim further comprising:

a secon-d timing capacitor coupled to both the input switch and output switch, the capacitor discharging when the input switch is closed,

a normally open secondy control switch coupled to the second timing capacitor,

the second control switch havinga thi-rdI input' terminal and being closed in response to an input signal applied` toy the third input terminal,

the second timing capacitor charging through the biasing resistor toward@ the predetermined first value of potential when the secondY control switch is closed, and

the;I holding means holding` the output switch in an4 open condition until thesecond capacitor charges to the predeterminedv secondvalue ofpotential.

12.. AnelectricalV circuit comprising: y

a normally` open rst transistor switch having a first inputA terminal, the first switch being. closed in response to an input signal` applied to the tirst input terminal,

a normally closedf second4 transistor switch coupled to the first switch,

a first and a second. timing capacitor coupled to both the: first. and. secondI switches, the capacitors dischargingwhen tlie rst switch is closed,

means coupled tothe. second switch for opening the vsecond switch in response to the closing of the first switch,

a biasing resistor coupled to both the rst and second switches,

a normally open third transistor switch coupledl to the rst timing capacitor, the third switch having a s'econd input terminar and being closed in response to an inputg signal applied to' the second'v terminal,

a normally open fourthL transistor-'switch coupled to the secondE timing capacitor, 'die'v fourth switch having a third' input terminal andy being closed in response to an input signal applied to the third terminal,

the first timing capacitor charging through the biasing resistor toward a predetermined rst value of potential when the third switch is closed,

the second timing capacitor charging through the biasing resistor toward the predetermined first value of potential when the fourth switch is closed, and

means coupled to the second switch for holding the 16 second switch in an open condition until at least one of the rstl and second capacitors charges to prey determined second value of potential.-

13. An electrical cirouitaccording to' claimlz in which the holding means comprises:

a iifth transistor switch, v

means coupled to the lifth switch for opening the fth switch in response to discharge of at least one ofthe lirst and second capacitors below a particular value of potential,

means coupled to the iifth switch for closing the fifth switch in response to the charging of at least one of the first and second capacitors to the predetermined second value of potential,

means coupled to the second for opening the second switch in response to the opening of the fifth switch, and Y means coupled to the second switch for closing the second switch in response toI the closing of the fifth switch.

14. An electrical switch comprising:

a normally open input switch having a first input terminal, the input switch being closed in response to an -input signal applied to the first input terminal,

a normally closed output switch coupled to the input switch,

a timing capacitor coupled to both the input switch and output switch, the capacitor discharging when the input switch is closed and charging when the input switch is open,

means coupled to the' output switch for opening the output switch in response to the closing of the input switch,

a biasing resistor coupledf to' both, the input switch and the output switch,

the Capacitor charging through the biasingresistor toward a predetermined rst value of potential,

means coupled to the output switch -for lholdin-'g the output switch in an open condition until the capacitor charges to a predetermined' second value of potential,

a normally open first control switch coupled to the holding means and having' -a second input terminal, the control switch being closed in responseto an input signalapplied to the se'condvv input terminal, and

means coupled to the output switch and including the holding means for holding the output switch in Van open condition Iunt-il the capacitor charges to a predetermined third val=ue of potential when' the first controll switch is closed.

15. An electrical circuit according to. claim: 14v further comprising:

a normally open second control switch eoupled'to the holding means and having al third input terminal, the second control switch being closedr in response to an input signal applied to the third` input terminal, and

means coupled to the output switch and includirgthe holding means for holding the output switch in an open condition unti-l the capacitor charges to a pre'- determined fourth value of potential when; the second control switch is closed.

16. An electrical switch comprising:

a normally open first transistor switch having' a first input terminal, the lirst switch being closed in response to an input signal applied to the rst input terminal,

a normally closed second transistor switch coupled to thelirst switch, Y

a timing capacitor coupled to both the lirst and second switches, the capacitor discharging whenr the first switch is closed and charging when the first switch is open, p

a biasing resistor coupled to both the first and second switches,

the capacitor charging through the biasing resistor toward a predetermined first value of potential,

a third transistor switch having at least one base element coupled to both the rst and second switches,

means coupled to the second switch for opening the second switch in response to the opening of the third switch,

means coupled to the second switch for closing the second switch in response to the closing of the th-ird switch,

fourth and fifth transistor switches both coupled to the third switch and having second and third input terminals, respectively,

the fourth switch being closed in response to an input signal applied to the second input terminal and the fth switch being closed in response to an input signal applied to the third input terminal,

means coupled to the third transistor switch for establishing a predetermined second value of potential at the base element of the third transistor switch when both the fourth and tifth switches are open, for establishing a predetermined third value of potential at the base element of the third transistor switch when the fourth switch is closed, and for establishing a predetermined fourth value of potential at the base element of the third transistor switch when the fth switch is closed, and

means coupled to the third transistor switch for opening the third transistor switch when the capacitor discharges below the potential established at the base of the third transistor and for closing the third transistor switch when the capacitor charges to a potential greater than that established at the base of the third transistor switch.

References Cited UNITED STATES PATENTS 3,045,187 7/1962 Belcastro 328-207 3,155,959 11/1964 Dobbie et al. 307-885 3,249,767 5/ 1966 Zeller 328-207 20 ARTHUR GAUSS, Primary Examiner.

B. P. DAVIS, Assistant Examiner. 

1. AN ELECTRICAL CIRCUIT COMPRISING: A NORMALLY OPEN INPUT SWITCH HAVING A FIRST INPUT TERMINAL, THE INPUT SWITCH BEING CLOSED IN RESPONSE TO AN INPUT SIGNAL APPLIED TO THE FIRST INPUT TERMINAL, A NORMALLY CLOSED OUTPUT SWITCH COUPLED TO THE INPUT SWITCH, MEANS COUPLED TO THE OUTPUT SWITCH FOR OPENING THE OUTPUT SWITCH IN RESPONSE TO THE CLOSING OF THE INPUT SWITCH, TIMING CIRCUIT MEANS COUPLED TO BOTH THE INPUT SWITCH AND THE OUTPUT SWITCH AND HAVING A FIRST AND A SECOND CONTROL CIRCUIT ELEMENT AND A SECOND INPUT TERMINAL, MEANS COUPLED TO THE OUTPUT SWITCH FOR MAINTAINING THE OUTPUT SWITCH IN ITS OPEN CONDITION FOR A PERIOD OF TIME GOVERNED BY THE TIMING CIRCUIT MEANS, MEANS COUPLED TO THE TIMING CIRCUIT MEANS FOR ISOLATING THE FIRST CONTROL CIRCUIT ELEMENT FROM THE REMAINDER OF THE TIMING CIRCUIT MEANS IN RESPONSE TO A FIRST SIGNAL APPLIED TO THE SECOND INPUT TERMINAL, AND 